Magnetic random access memory (MRAM) cells have been an object of renewed interest with the discovery of magnetic tunnel junctions (MTJs), having a strong magnetoresistance at ambient temperature. These MRAM cells present many advantages such as speed (a few nanoseconds of duration of writing and reading), non-volatility, and insensitivity to ionizing radiations. Consequently, MRAM cells are increasingly replacing memory that uses more conventional memory cell technology based on the charge state of a capacitor (DRAM, SRAM, FLASH).
Thermally-assisted switching magnetic tunnel junction (TAS-MTJ)-based MRAM cells have been described in U.S. Pat. No. 6,950,335 B2 and United States Patent Application Publication No. US 2006/0291276 A1. These typical implementations use a first dedicated line for the magnetic field generation and a second, separate dedicated line for heating the cell junction or reading the cell state.
FIG. 1a shows a first implementation of a conventional TAS-MTJ based MRAM cell 1. As illustrated in FIG. 1, the cell 1 comprises a junction 2 placed between a selection CMOS transistor 3 and a bit line 4, represented parallel to the page. Also orthogonal with the bit line 4, a field (or writing) line 5 is placed underneath the magnetic tunnel junction 2. This configuration includes a strap 7 between the bottom of the magnetic tunnel junction 2 and the selection transistor 3. More particularly, the field line 5 uses an M2 CMOS metal level, and two M1 metal lines are used to contact select transistor source/drain (S/D) nodes. The bit line 4 is at an M3 CMOS level. The cell configuration of FIG. 1a requires, at the M2 level, a minimum spacing d between the field line 5 and the cell strap 7, increasing the size of the cell 1. Using the bottom part of the magnetic tunnel junction 2 as a strap 7 can further increase the distance between two adjacent cells 1, due to a minimum spacing requirement between adjacent straps 7.
The writing procedure of the TAS-MTJ based MRAM cell 1 is performed by heating the magnetic tunnel junction 2 with a heating current 31 that passes through the magnetic tunnel junction 2 via the bit line 4. This is achieved when the transistor 3 is in a conducting mode (ON). Simultaneously (or after a short time delay) and once the magnetic tunnel junction 2 has reached a suitable temperature threshold, a field current 41 is passed through the field line 5, producing a magnetic field 42 capable of addressing the magnetic tunnel junction 2 by switching the magnetization of a soft magnetic layer, or storage layer (not shown), into the appropriate direction. The heating current 31 then is turned off by setting the selection transistor 3 in a cutoff mode (OFF) or by removing the transistor's source-drain bias. The field current 41 is maintained during the cooling of the magnetic tunnel junction 2. The field current 41 is switched off when the magnetic tunnel junction 2 has reached a predetermined temperature, wherein the magnetization of the storage layer is frozen in the written state.
FIG. 1b shows an alternative configuration of the conventional TAS-MTJ based MRAM cell 1, wherein the field line 5 is placed above the magnetic cell 1. In the configuration of FIG. 1b, the field line 5 uses an M3 CMOS metal level. The bit line 4 is disposed at an M2 CMOS level with the magnetic tunnel junction 2 being placed between the M1 and M2 levels. This configuration allows for an increased density, or a reduced cell size, since the strap 7 of configuration of FIG. 1a is not required and since the cell 1 can be stacked on the transistor 3. The procedure for writing to the cell 1 of FIG. 1b is similar to the procedure for writing to the cell 1 of FIG. 1a. However, the larger distance h between the M3 level and the magnetic tunnel junction 2 requires the use of a field current 41 to write the cell 1 of FIG. 1b that is typically at least double the field current 41 used to write the cell 1 of FIG. 1a. Both cell configurations of FIG. 1a and FIG. 1b also require at least three CMOS metal levels.
Accordingly, there is a need for a TAS-MTJ based MRAM cell having lower power consumption and for memory devices comprising an array of TAS-MTJ based MRAM cells with higher cell density and lower cost of fabrication.